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NXP Semiconductors /LPC11E6x /CT16B0 /TCR

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Interpret as TCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)CEN 0 (NOP)CRST 0RESERVED

CRST=NOP, CEN=DISABLED

Description

Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

Fields

CEN

Counter enable.

0 (DISABLED): The counters are disabled.

1 (ENABLED): The Timer Counter and Prescale Counter are enabled for counting.
CRST

Counter reset.

0 (NOP): Do nothing.

1 (RESET): The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data